1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor integrated circuit having a fuse circuit and a method of driving the same.
2. Description of the Related Art
Generally, a repairing defects and changing setting value of the semiconductor integrated circuit (IC) are performed through a fuse programming method.
The fuse programming method may include a programming method for cutting-off the fuse by supplying an over-current, a programming method for cutting-off or connecting the fuse through applying a laser beam, and a programming method for using an erasable programmable read only memory (EPROM). The programming method through applying the laser beam may be more simple and may have a low error probability so that is generally used. However, the programming method through applying the laser beam is performed in a wafer state of the semiconductor IC. Herein, the wafer state of the semiconductor IC is a step prior to the step in which the semiconductor IC is fabricated to a package. Due to the above-mentioned reasons, the programming method through applying the laser beam may be difficult to be used to the package state. Thus, in the package state, an anti-fuse may be used to repair defects in the semiconductor IC.
Since the anti-fuse has electrical characteristics opposite to those of a fuse, the anti-fuse may be simply programmed in the package state. Specifically, the anti-fuse is a resistive fuse that has a high resistance of, for example, 100 MΩ before a program operation and has a low resistance of, for example, 100 KΩ or lower after the program operation. That is, the anti-fuse has a capacitance before the program operation and has a resistance after the program operation when the anti-fuse is a transistor of which a source and a drain are electrically coupled. The anti-fuse may be typically formed of a very thin dielectric material, such as a composite formed by interposing a dielectric material, such as SiO2, silicon nitride, tantalum oxide, or silicon dioxide-silicon nitride-silicon dioxide (ONO), between two conductive materials. During the program operation of the anti-fuse, a high voltage of, for example, about 10V is applied to anti-fuse terminals for a sufficient time to destroy the dielectric material. Thus, when the anti-fuse is programmed, an electrical short occurs between the two conductive materials of the anti-fuse, thereby reducing the resistance of the anti-fuse.
FIG. 1 is a block diagram illustrating a fuse circuit in accordance with a conventional art.
Referring to FIG. 1, a unit fuse circuit E-FUSE SET includes a driving unit 11, an electrical fuse 13 and a sensing unit 15. The driving unit 11 drives a sensing node SN to a high voltage VRUPTURE in response to a rupture enable signal RUP_EN and a rupture address RUP_ADD. The electrical fuse 13 is coupled between the sensing node SN and a ground voltage VSS terminal. The sensing unit 15 generates a fuse state signal FUSE_OUT by sensing a rupture state or resistive state of the electrical fuse 13 coupled with the sensing node SN using a sensing voltage VSENSING.
The driving unit 11 includes a NAND gate and a PMOS transistor. The NAND gate performs a logic NAND operation of rupture enable signal RUP_EN and the rupture address RUP_ADD. A gate of the PMOS transistor is coupled to an output of the NAND gate, a source and a drain are coupled to the high voltage VRUPTURE and the sensing node SN. Herein, the high voltage VRUPTURE may be high voltage level as much as the electrical fuse 13 is ruptured, for example, the high voltage VRUPTURE includes a pumping voltage VPP generated inside the semiconductor IC 200 or applied from an external.
The electrical fuse 13 includes the anti-fuse ruptured by a voltage difference between the sensing node SN and the ground voltage VSS terminal.
The sensing unit 15 outputs an initialized fuse state signal FUSE_OUT in response to a power up signal PWRUP, and changes or maintains a logic level of the fuse state signal FUSE_OUT according to whether or not the electrical fuse 13 is ruptured. Meanwhile, the sensing unit 15 uses the sensing voltage VSENSING as a source voltage, and the sensing voltage VSENSING may include a power supply voltage VDD.
FIG. 2 is a block diagram implemented with the unit fuse circuit in FIG. 1 as an array structure.
Referring to FIG. 2, the fuse set array 100 includes a plurality of unit fuse circuits E-FUSE SET<0:n>. A description of plurality of unit fuse circuits E-FUSE SET<0:n> has been described with reference to FIG. 1, so a description thereof will be omitted for the sake of convenience. The plurality of E-FUSE SET<0:n> commonly receives the common enable signal RUP_EN and the power up signal PWRUP and separately receives a plurality of addresses RUP_ADD<0:n>.
That is, the above fuse set array 100 commonly receives the common enable signal RUP_EN, the high voltage VRUPTURE, and the sensing voltage VSENSING, so that it is possible to increase an area efficiency occupied by chip.
However, the fuse set array 100 as above has the following concern.
The electrical fuse 13 is ruptured by an electrical stress in the package state, so that the unit fuse circuit E-FUSE SET cannot normally output the fuse state signal FUSE_OUT due to the electrical stress such as a voltage, a current and a time. That is to say, after electrical fuse 13 is ruptured, it may be difficult to have an exact resistance by applying the electrical stress, so that the FUSE_OUT may not be output normally. On the contrary, the electrical fuse 13 is ruptured by applying the electrical stress without intension, the state signal FUSE_OUT may not be output normally. When electrical fuse 13 is ruptured without intension, the electrical fuse 13 is not restored on its characteristic.
Specially, when the high voltage VRUPTURE and the sensing voltage. VSENSING are commonly used as a source voltage in one unit fuse circuit E-FUSE SET, the unit fuse circuit E-FUSE SET is in a stressful environmental.